The present invention relates to a switched-capacitor amplifier circuit for reducing output variations.
Switched-capacitor amplifier circuit techniques for reducing output variations and alleviating the requirements placed on the slow rate of an operational amplifier have been heretofore reported. Such a switched-capacitor amplifier circuit is described by Haug, K., Temes, G. C., and Martin, K. W., in "Improved Offset-Compensation Schemes for Switched-Capacitor Circuits", Proceeding of IEEE International Symposium on Circuits and Systems, pp. 1054-1057, 1984 (hereinafter referred to as paper 1).
A conventional switched-capacitor amplifier circuit is shown in FIG. 5. Clock voltage, input voltage, and output voltage used in this switched-capacitor amplifier circuit are shown in FIGS. 6(a)-(c), where the value of the output voltage Vout at sampling phase .phi..sub.1 is almost equal to the value assumed at the previous clock pulse .phi..sub.2 where the input voltage Vin varies mildly. That is, the value of the output voltage is kept almost constant.
In the circuit of FIG. 5, a capacitor 4 is used to sample the input voltage. A capacitor 2 is used to amplify and deliver the sample input voltage. The gain is the ratio of the capacitance of the capacitor 4 to the capacitance of the capacitor 2. Another capacitor 3 is used to provide negative feedback to the operational amplifier 1 on clock pulse .phi..sub.2.
Switching circuits 6, 8, and 10 are closed at sampling phase .phi..sub.1 (FIG. 6(a). The input voltage Vin (FIG. 6(b)) is stored as electric charge in the capacitor 4. The capacitor 2 is discharged via the switching circuit 8. The capacitor 3 is connected between the input and output terminals of the operational amplifier 1 to provide negative feedback to this amplifier.
During the phase .phi..sub.2, the output is valid, and the switching circuits 6, 8, and 10 are opened, while the switching circuits 7, 9, and 11 are closed. At this time, the charge stored in the capacitor 4 is transferred to the capacitor 2. The output Vout (FIG. 6(c)) that is the product of the gain (that is given by the ratio of the capacitance of the capacitor 2 to the capacitance of the capacitor 4) and the input voltage Vin is produced at an output terminal 14.
At the next sampling phase .phi..sub.1, new input voltage is stored as electric charge in the capacitor 4. At this time, electric charge is transferred from the capacitor 4 to the capacitor 3 via the switching circuit 6 according to the magnitude and polarity of the input voltage Vin. At the same time, electric charge stored in the capacitor 2 is released at .phi..sub.1 and transferred to the capacitor 3 via the switching circuit 6. Where the frequency of the input signal is much smaller than the clock frequency, the electric charges transferred from the capacitors 2 and 4 to the capacitor 3 are opposite in polarity but almost identical in amount. Therefore, these electric charges cancel out. Consequently, the output voltage Vout at the sampling phase .phi..sub.1 is almost equal to the output voltage at the valid phase .phi..sub.2.
Another switched-capacitor amplifier circuit is described in a paper presented by Gregorian, R., Martin, K., Temes, G. C., in "Switched Capacitor Circuit Design", Proceedings of IEEE, Vol. 71, pp.941-966, 1983. This circuit is shown in FIG. 8. Clock voltage, input voltage, and output voltage used in this circuit are shown in FIGS. 9(a)-(c), where the output voltage Vout returns to 0 V at every sampling phase .phi..sub.1 when the input voltage Vin varies mildly.
Switching circuits 6, 8, and 10 are closed at sampling phase .phi..sub.1 (FIG. 9(a)). The input voltage Vin (FIG. 9(b)) is stored as electric charge in a capacitor 4. A capacitor 2 is discharged through the switching circuit 8. The switching circuit 6 is connected between the input and output terminals of the operational amplifier 1 to provide negative feedback to the amplifier 1. At the sampling phase .phi..sub.1, the switching circuit 6 is closed and so the potential at the output terminal 14 becomes equal to the potential at a virtual grounding terminal 15.
During the phase .phi..sub.2, the output is valid, and the switching circuits 6, 8, and 10 are opened, while the switching circuits 9 and 11 are closed. At this time, the charge stored in the capacitor 4 is transferred to the capacitor 2. The output Vout (FIG. 9(c)) that is the product of the gain (that is given by the ratio of the capacitance of the capacitor 2 to the capacitance of the capacitor 4) and the input voltage Vin is produced at an output terminal 14.
At the next sampling phase .phi..sub.1, a new input voltage is stored as electric charge in the capacitor 4. The switching circuit 6 is again closed. The potential at the output terminal 14 becomes equal to the potential at a virtual grounding terminal 15. In this way, in this circuit, the output voltage Vout becomes equal to the virtual grounding potential at every sampling phase .phi..sub.1. Therefore, the output voltage Vout varies greatly. Hence, the slow rate of the operational amplifier is required to be set large.
In the conventional switched-capacitor amplifier circuit (FIG. 5) described in the aforementioned paper 1, the output voltage at the sampling phase .phi..sub.1 is almost equal to the output voltage at the valid phase .phi..sub.2. Therefore, the requirement, i.e., the slow rate of the operational amplifier must be set large, can be mitigated.
In the conventional switched-capacitor amplifier circuit shown in FIG. 5, if the frequency of the input signal is considerably lower than the sampling frequency as shown in FIG. 6(b), electric charges transferred from the capacitors 2 and 4 to the capacitor 3 are opposite in polarity at clock pulse .phi..sub.1 but equal in amount. Therefore, these charges cancel out. The output voltage Vout hardly varies. However, as the frequency of the input signal rises as shown in FIG. 7(b), the amounts of electric charge transferred from the capacitors 2 and 4 to the capacitor 3 at clock pulse .phi..sub.1 (FIG. 7(a)) produce a greater difference. This difference appears as output voltage Vout (FIG. 7(c)) at output terminal 14 through the capacitor 3. In consequence, the output voltage Vout at sampling phase .phi..sub.1 varies to a larger extent. The result is that the output produces an error.
In the conventional switched-capacitor amplifier circuit shown in FIG. 5, it is assumed that the positive power-supply voltage is 1.5 V, the negative power-supply voltage is -1.5 V, and the analog ground is 0 V. For simplicity, it is assumed that the capacitors 2, 3, and 4 have the same capacitance of C. Clock pulses, input voltage, and output voltage are shown in FIG. 6. When the input voltage is -1.0 V at clock pulse .phi..sub.1, the electric charge stored in the capacitor 4 is given by EQU Q.sub.4 =C.times.(0 V-(-1.0 V)) =C.times.(1 V)
Electric charge stored in the capacitor 2 is given by EQU Q.sub.2 =C.times.(0 V-0 V)) =0
Meanwhile, electric charge stored in the capacitor 3 is given by EQU Q.sub.3 =C.times.(0 V-Vout)
At the next clock pulse .phi..sub.2, the capacitor 4 discharges, and the positive charge stored on the side of the virtual grounding terminal 15 of the capacitor 4 is transferred to the capacitor 2. Therefore, the voltage developed across the capacitor 2 is given by EQU V.sub.2 =Q.sub.4 /C =1 V
Thus, the output voltage Vout is EQU Vout=0 V-V.sub.2 =0 V-1 V =-1 V
In this way, an output voltage equal to the input voltage is obtained.
Electric charge stored in the capacitor 3 is given by EQU Q.sub.3 =C.times.(0 V-Vout) =C.times.(1 V)
If the input voltage is 1.0 V at the next clock pulse .phi..sub.1, electric charge corresponding to EQU C.times.(1.0 V-0 V) EQU C.times.(1 V)
is transferred from the capacitor 4 to the capacitor 3. At the same time, the capacitor 2 discharges, and its electric charge is fully transferred from the capacitor 2 to the capacitor 3. The amount of charge correspond t o EQU C.times.V.sub.2 =C.times.(1 V)
Since electric charge corresponding to C.times.(1 V) was stored in the capacitor 3 at clock pulse .phi..sub.2, electric charge corresponding to C.times.(3 V) is stored in the capacitor 3. Therefore, the output voltage goes toward EQU Vout=0 V-3 V=-3 V
Since the output from the operational amplifier 1 cannot decrease below the negative power-supply voltage of -1.5 V, the potential at the virtual grounding terminal 15 shifts in the forward direction from analog ground 0 V. Consequently, the charge stored in each capacitor at clock pulse .phi..sub.1 deviates greatly from the ideal value. For this reason, electric charge is not precisely transferred at the next clock pulse .phi..sub.2. As a result, the output voltage Vout involves a great error.